This invention relates to using configuration registers in an integrated circuit and more particularly to providing a Local Register Network that reads and writes to a distributed configuration register architecture.
Application specific integrated circuits (ASICs) typically have multiple logic circuits arranged into functional blocks. The functional blocks are located in different places on the integrated circuit substrate. Each functional block may include one of more configuration registers that retain status information and control the operations preformed in the logic circuit.
The configuration registers are typically programmed at ASIC start-up by a central processing unit (CPU) through a primary bus having data and address lines. The CPU loads the configuration registers with configuration data according to the functions that the CPU wants the ASIC to perform. The CPU later reads some or all of the configuration registers for specified functional blocks to determine the operational status of the ASIC.
The ASIC typically includes a central decoder that decodes each configuration register address sent by the CPU. The central decoder maps the address to one of the configuration registers located in a centrally located register block. The enabled register is either loaded with data from the data lines in the primary bus or outputs currently stored status information onto the data lines. All configuration registers and the configuration register decoder are located in the same central location on the ASIC.
The logic circuits associated with the different configuration registers are spread out over the entire ASIC. There are usually numerous configuration registers connected to each distributed functional block. A substantial amount of area on the ASIC die is used for routing the data and control lines to each configuration register. Data traffic to and from configuration registers is generally less time critical and utilizes less bandwidth than the data traffic between the logic circuits and main memory. However, a large portion of the interconnections on the ASIC are used for passing information to and from the configuration registers.
The configuration register interconnections substantially increase the complexity of routing ASIC circuits and utilizes a large portion of the area on the ASIC die. This impacts die size along with the time required to design a routing layout for interconnections in the ASIC. Thus, the cost and time to get the ASIC to market is substantially increased.
Since one central decoder is used to enable all configuration registers in the ASIC, the decoder circuitry is complex. As more configuration registers are used in the ASIC, the complexity of the decoder circuitry substantially increases, further increasing the routing resources and routing time required to interconnect the distributed logic blocks to the configuration register circuitry.
Accordingly, a need exists for reducing the complexity of circuitry and the number of interconnections needed to control configuration registers.